The present invention relates to an active matrix liquid crystal display and a method of driving the display, suitable for use in various data terminals and television sets, and in particular, relates to an active matrix liquid crystal display and a method of driving the display which allow for improvement of display quality and reduction of power consumption.
The liquid crystal display of active matrix drive mode is an example of conventionally known image displays. As shown in FIG. 16, the liquid crystal display is composed of a liquid crystal panel 1, a scan line drive circuit 2, and a signal line drive circuit 3.
The liquid crystal panel 1 includes a matrix substrate 7, an opposite substrate 8, and liquid crystal (not shown) injected between the substrates 7, 8. The opposite substrate 8 is disposed parallel to the matrix substrate 7. On the matrix substrate 7 are there provided signal lines S(1) to S(I) and scan lines G(1) to G(J) that cross each other, as well as display cells P arranged in a matrix. On the opposite substrate 8, an opposite electrode 13 shown in FIG. 17 is provided commonly to all the display cells P.
As shown in FIG. 17, each display cell P has a thin film transistor (TFT) 11, which is a switching element, and a liquid crystal capacitance CLC. As shown also in FIG. 18, the TFT 11 is connected at its source to the signal line S(i) and at its gate to the scan line G(j). The signal line drive circuit 3 supplies, to a signal line S(i), a source signal Vs which is then transmitted through the source and drain of the TFT 11 and applied as a drain voltage Vd(i,j) to a display electrode 12 which is one of the electrodes of the liquid crystal capacitance CLC. A common signal Vcom is applied to an opposite electrode 13 which is the other electrode of the liquid crystal capacitance CLC. Thus, a difference between the drain voltage Vd(i,j) and the common signal Vcom is applied to the liquid crystal capacitance CLC. As a result, the transmittance or reflectance of liquid crystal 14 sandwiched between the electrodes 12, 13 so changes that an image is displayed by the display cells P in accordance with incoming image data. Switching off the TFT 11 does not cause the displayed image to change immediately, since in the display cell P the charge accumulated in the liquid crystal capacitance CLC is held for a specified period of time.
In liquid crystal displays, liquid crystal would deteriorate in terms of characteristics under continuous application of d.c. voltage to the liquid crystal; to avoid the inconvenience, the liquid crystal is driven by a voltage that changes from positive to negative and vice versa. The method of driving by means of xe2x80x98inversion drive voltagexe2x80x99 is generally termed inversion drive. Different forms of inversion include frame inversion, source line inversion, gate line inversion, and dot inversion.
Assume that the foregoing liquid crystal display is driven by frame inversion drive.
FIG. 19 describes, by means of waveform, development of drive voltages applied to display cells P in the liquid crystal panel 1: namely, the display cell P(i,1) located in the i-th column, 1st row, the display cell P(i,j) centrally located in the i-th column, j-th row, and the display cell P(i,J) located in the i-th column, J-th row. For the purpose of simple description, the figure shows an example in which the source signal Vs is steady at 2 V and the common signal Vcom alternates by a 4 V amplitude to create xc2x12 V drive voltages for application to the display cells P.
Referring to the display cell P(i,1) in the top row, the source signal Vs is written as the TFT 11 is switched on by a gate pulse fed through the scan line G(1) at point A1. With the TFT 11 switched off later, the voltage across the liquid crystal 14 does not change because of the presence of the liquid crystal capacitance CLC. Subsequently, the common signal vcom goes negative at point R, varying by an amount equal to the aforementioned amplitude, and the drain voltage Vd varies by the same amount because of the principle of conservation of charge. The source signal Vs is written again as the TFT 11 is switched on by another gate pulse supplied to the scan line G(1) at point B1; the voltage across the liquid crystal 14 is retained. The writing and retaining recurs with a period T in this manner in the display cell P(i,1).
Referring to the central display cell P(i,j), the source signal Vs is written as the TFT 11 is switched on by a gate pulse fed through the scan line G(j) at point Aj; the voltage across the liquid crystal 14 is retained. Subsequently, the common signal Vcom goes negative at point R, varying by an amount equal to the aforementioned amplitude, and the drain voltage Vd varies by the same amount accordingly. The source signal Vs is written again as the TFT 11 is switched on at point Bj; the voltage across the liquid crystal 14 is retained. The writing and retaining recurs in this manner in the display cell P(i,j) similarly to the foregoing.
Referring to the display cell P(i,J) in the bottom row, the source signal Vs is written as the TFT 11 is switched on by a gate pulse fed through the scan line G(J) at point AJ; the voltage across the liquid crystal 14 is retained. Subsequently, the common signal Vcom varies by an amount equal to the aforementioned amplitude at point R, and the drain voltage Vd varies by the same amount. The source signal Vs is written again at point BJ; the voltage across the liquid crystal 14 is retained. The writing and retaining recurs in this manner in the display cell P(i,J) similarly to the foregoing.
As detailed above, the variation of the drain voltage Vd is equal to that of the common signal Vcom. Put it differently, the relative value of the drive voltage VLC(i,1) to the common signal Vcom is invariable, for example, in the display cell P(i,1). This makes it possible to drive the display cell (i,1) alternately with voltages xc2x12 V. The same description holds true with the other display cells P(i,j) and P(i,J).
Now, the following will describe a case where the common signal Vcom is a steady, d.c., voltage.
FIG. 20 describes, by means of waveform, development of drive voltages applied to display cells P in the liquid crystal panel 1: namely, the display cell P(i,1) located in the i-th column, 1st row, the display cell P(i,j) centrally located in the i-th column, j-th row, and the display cell P(i,J) located in the i-th column, J-th row. For the purpose of simple description, the figure shows an example in which the common signal Vcom is steady at 2 V and the source signal Vs alternates by a 4 V amplitude to create xc2x12 V drive voltages for application to the display cell P.
According to this drive scheme, the common signal Vcom does not alternate between positive and negative voltage levels. Therefore, the common signal Vcom does not vary in amplitude, nor does the drain voltage Vd. Further, in a liquid crystal cell P depicted by means of an equivalent circuit in FIG. 17, a change in polarity of the source signal Vs does not lead to a change in polarity of the drain voltage Vd.
Generally, liquid crystal displays require a backlight as a light source, since liquid crystal itself does not emit light by nature. The lamp for the backlight is highly power consuming and makes it difficult to fabricate a power efficient crystal liquid display. In contrast, recently developed reflective displays do not require a backlight and are used in mobile data terminals and other like devices that are mostly used outdoors.
Electrodes used in some liquid crystal displays of this kind have a reflective electrode structure. Some liquid crystal displays employ an alternative structure in which pixel electrodes (reflective electrodes) and bus lines, such as signal lines, are provided in different layers separated by an interlayer insulating film.
In a reflective electrode structure, as shown in FIG. 22, a reflective electrode 12a, as a display electrode 12, is positioned to overlap, along its periphery, mutually adjacent signal lines S(i), S(i+1) and scan lines G(jxe2x88x921), G(j). The structure allows no gap to form between the reflective electrode 12a and the signal lines S(i), S(i+1) and the scan lines G(jxe2x88x921), G(j), thereby preventing light leakage.
FIG. 21 shows an equivalent circuit of the display cell P having the reflective electrode structure. The equivalent circuit includes, as well as the liquid crystal capacitance CLC, parasitic capacitances Csd1, Csd2, Cgd1, Cgd2. The parasitic capacitances Csd1, Cgd2 are found between the drain of the TFT 11 and the signal line S(i) and between the drain and the scan line G(jxe2x88x921) respectively. The parasitic capacitances Csd2, Cgd1 are found between the drain of the TFT 11 and the signal line S(i+1) and between the drain and the scan line G(j) respectively.
However, problems arise if the frame inversion drive laid out in the foregoing is applied to the liquid crystal panel 1 having the reflective electrode structure or the above structure in which pixel electrodes and bus lines are provided in different layers. See Japanese Examined Patent Publication No. 5-2208/1993 (Tokukohei 5-2208; published on Jan. 12, 1993).
FIG. 23 describes, by means of waveform, development of drive voltages applied to display cells P, namely, the display cell P(i,1) in the i-th column, 1st row, the central display cell P(i,j) in the i-th column, j-th row, and the display cell P(i,J) in the i-th column, J-th row, in the liquid crystal panel 1 with a reflective electrode structure. For the purpose of simple description, the figure shows, similarly to FIG. 19, an example in which the source signal Vs is 2 V (DC) and the common signal Vcom is 4 V (AC).
In the example of FIG. 19, if the display cell P is retaining the voltage across the liquid crystal, a variation in amplitude of the common signal Vcom leads to a similar variation in amplitude of the drain voltage Vd. This is however not the case with the example of FIG. 23, in which charges are redistributed among the parasitic capacitances Csd1, Csd2, Cgd1, Cgd2. The variation, xcex94Vd1, of the drain voltage Vd1 is given by equation (1):
xcex94Vd1=(CLC/CD)xc3x97Vac1xe2x80x83xe2x80x83(1)
where CD is a total capacitance connected to the drain electrode of the TFT 11 (=CLC+Csd1+Csd2+Cgd1+Cgd2) and Vac1 is a variation of the common signal Vcom.
The voltage retained by the liquid crystal cell P after the common signal Vcom has changed is lower than the otherwise retained standard voltage Vx1 by a fall voltage Vy1 (=Vac1xe2x88x92xcex94Vd1).
Referring to FIG. 23, a voltage is written to, and a standard voltage Vx1 is retained by, the display cell P during a retaining period Ttrue(j). A change in polarity of the common signal Vcom during a falling period Tfalse(j) leads to a xcex94VD1 drop in the voltage of the display cell P from the standard voltage. Thus, the display cells P(i,1), P(i,j), P(i,J) have different retaining periods Ttrue(1), Ttrue(j), Ttrue(J) and different falling periods Tfalse(1), Tfalse(j), Tfalse(J).
Specifically, the drive voltage VLC(i,1) in the top row remains low, if ever, for a short falling period Tfalse(1) under the effect of the common signal Vcom, since only writing of a voltage is performed immediately afterwards. In contrast, with a change in polarity of the common signal Vcom immediately after the writing, the drive voltage VLC(i,J) in the bottom row remains low for a long falling period Tfalse(J) extending from the change in polarity to the start of a next round of writing.
Each period for writing and retaining for one screen is made of a first period Ta1 extending from the start of the scanning (writing) of the top row to the end of the scanning (writing) of the bottom row, a second period Tb1 extending from the end of the scanning of the bottom row to the polarity change of the common signal Vcom, and a third period Tc1 extending from the polarity change of the common signal Vcom to the start of a next round of scanning. The drive voltage VLC(i,1) for the top row remains equal to the standard voltage Vx1 during the first and second periods Ta1, Tb1 and is lower than the standard voltage Vx1 by the fall voltage Vy1 in the third period Tc1. The effective value, VLCrms(i,1), of the drive voltage VLC(i,1) is given by
xe2x80x83VLCrms(i,1)={((Ta1+Tb1xc2x7Vx12+Tc1xc2x7(Vx1xe2x88x92Vy1)2)/(Ta1+Tb1+Tc1)}1/2
The drive voltage VLC(i,J) for the bottom row remains equal to the standard voltage Vx1 during the second period Tb1 and falls from the standard voltage Vx1 by the fall voltage Vy1 in the first and third periods Ta1, Tc1. The effective value, VLCrms(i,J) of the drive signal VLC(i,J) is given by
VLCrms(i,J)={(Tb1xc2x7Vx12+(Ta1+TC1)xc2x7(Vx1xe2x88x92Vy1)2)/((Ta1+Tb1+TC1)}1/2
Here, Vx1=2 V, Vac1=4 V, CLC=4.7 pF, Csd1+Csd2+Cgd1+Cgd2=0.3 pF, CD=5 pF, Ta1=15 mS, Tb1=0.5 mS, and Tc1=0.5 mS. Accordingly, VLCrms (i,1)=1.993 Vrms and VLCrms(i,J)=1.768 Vrms. The two effective values have a difference of 0.225 Vrms, which means that the effective value of the drive voltage for the display cell P varies 0.225 Vrms, when comparing the top to the bottom of the screen. The difference in the voltage is the cause of unequal brightness between the top and the bottom of the display screen.
The problem does not occur if the common signal Vcom is fixed to a constant d.c. voltage and is thus invariable as mentioned earlier in reference to FIG. 20. However, with the display cell P having a reflective electrode structure of FIG. 21, the source signal Vs changes in polarity with respect to the common signal Vcom for every frame as shown in FIG. 24; therefore the display cells P(i,1), P(i,j), P(i,J) have the periods Tfalse(1), Tfalse(j), Tfalse(J) respectively, which leads to unequal brightness of the display screen similarly to the foregoing case.
With these display cells P, if the source signal Vs changes in polarity with a constant drive voltage VLC, charges are redistributed among the parasitic capacitance Csd1, Csd2, Cgd1, Cgd2. Therefore, the display electrode 12 is affected by the parasitic capacitances Csd1, Csd2 located between the drain electrode and the two adjacent signal lines S(i), S(i+1). The variation, xcex94Vd2, of the drain voltage Vd2 is given by equation (2):
xcex94Vd2={(Csd1+Csd2)/CD}xc3x97Vac2xe2x80x83xe2x80x83(2)
where CD is a total capacitance connected to the drain electrode (=CLC+Csd1+Csd2+Cgd1+Cgd2) and Vac2 is a variation of the source signal Vs.
The voltage retained by the display cell P after the source signal Vs has changed is lower than the otherwise retained voltage by xcex94Vd2. The falling periods Tfalse(1), Tfalse(j), Tfalse(J) which occur due to the voltage fall differ in length as mentioned earlier.
Attention should be paid to that: (i) the drive voltage VLC is not absolute, but always relative to the common signal Vcom; and (ii) if the common signal Vcom changes in polarity, a change in the common signal Vcom leads to a similar change in the potentials (drain potentials) of the opposite electrode 13 and the opposing display electrode 12, and the drive voltage VLC is therefore invariable. The aforementioned inconvenience due to the change in polarity of the common signal Vcom is caused by the common signal Vcom that varies differently depending upon the parasitic capacitances Csd1, Csd2, Cgd1, Cgd2.
If the common signal Vcom is a constant voltage, the common signal Vcom is invariable, and the drain voltage Vd varies depending upon the parasitic capacitance Csd1, Csd2 when the source signal Vs varies. Therefore, undesirable variations of the drive voltage VLC occur.
Each period for writing and retaining for one screen is made of the aforementioned first period Ta1, second period Tb1, third period Tc1. The drive voltage VLC(i,1) for the top row remains equal to the standard voltage Vx1 during the first and second periods Ta1, Tb1 and falls from the standard voltage Vx1 by vy1 (=xcex94Vd2) in the third period Tc1. The effective value, VLCrms(i,1), of the drive voltage VLC(i,1) is given by
VLCrms(i,1)={((Ta1+Tb1)xc2x7Vx12+Tc1xc2x7(Vx1xe2x88x92Vy1)2)/(Ta1+Tb1+Tc1)}1/2
The drive voltage VLC(i,J) for the bottom row remains equal to the standard voltage Vx during the second period Tb1 and is equal to the difference between the standard voltage Vx1 and the source signal Vd during the first and third periods Ta1, Tc1. Therefore, the effective value, VLCrms(i,J), of the drive signal VLC(i,J) retained by the display cell P(i,J) is given by
VLCrms(i,J)={(Tb1)xc2x7Vx12+(Ta1+Tc1)xc2x7(Vx1xe2x88x92Vy1)2/(Ta1+Tb1+Tc1)}1/2
Here, Vx1=2 V, Vac2=4 V, CLC=4.7 pF, Csd1+Csd2+Cgd1+Cgd2=0.3 pF, CD=5 pF, Csd1+Csd2=0.15 pF, Ta1=15 mS, Tb1=0.5 mS, and Tc1=0.5 mS. Accordingly, VLCrms(i,1)=1.996 Vrms and VLCrms(i,J)=1.884 Vrms. The two effective values have a difference of 0.112 Vrms, which means that the effective value of the drive voltage for the display cell P varies 0.112 Vrms, when comparing the top to the bottom of the screen. The difference in the voltage is the cause of unequal brightness between the top and the bottom of the display screen.
An objective of the invention is to offer an active matrix liquid crystal display and a method of driving the display which allows for reducing the aforementioned difference in brightness that occurs between the top and bottom of the display screen in frame inversion drive.
An active matrix liquid crystal display and a method of driving the display in accordance with the present invention, in order to achieve the objective, are such that:
active elements provided for respective, matrix-forming display cells scan the display cells a scan line at a time for selection;
a signal voltage is written to display electrodes in selected ones of the display cells;
a drive voltage determined by the signal voltage and a common voltage is applied across liquid crystal by applying the common voltage to an opposite electrode positioned opposite to the display electrodes; and
either one of the common voltage and the signal voltage changes in polarity with respect to the common voltage in each frame,
wherein:
non-scanning means provides a non-scan period during which the signal voltage is retained and no new signal voltage is written, immediately following a scan period in which the signal voltage is written to some of the display cells corresponding to one screen, the non-scan period being equal to or longer than the scan period; and
inversion control means changes either one of the common voltage and the signal voltage in polarity with respect to the signal voltage in the non-scan period.
In frame inversion drive, as mentioned earlier, the parasitic capacitance that develops in the display cell have negative effects: for example, the effective value of the voltage applied across the liquid crystal falls. The effects vary from line to line of the display screen, and this leads to irregular brightness of the display image. To address these problems, a non-scan period which is equal to or longer than the scan period is provided immediately following the scan period, and this causes the display cells to retain a standard drive voltage during the non-scan period. The difference in effective value of the voltage level applied to the display cells is greatly reduced between the top and bottom rows of the display screen, and the difference in brightness between these two rows are in practice eliminated.
For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.